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Please find the below requirements and request you to share your
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Work Location:hyderabad
Verification:
Requirements
Key Responsibilities:
• Responsible for participating in the pre-silicon blocks,
chip, multi-chip and system level verification strategy for the
Graphics chips
• Specifying an overall design verification plan for full
chip SoC
• Specifying or reviewing verification plans for complex
blocks within the ASIC
• Architecting new verification methodologies and evaluating
new tools.
• Responsible for developing complex verification environment
using the latest coverage/assertions based verification design
methodology, which includes :
o self-checking, reusable, automated verification environment :
both at full-chip & block level
o Constrained random generators and reference models
• Being a mentor and technical leader for more junior
verification engineers.
• Leading or participating in the ASIC bring-up and debug
Job Requirements and Skills:
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics
Engineering
• Minimum 5+ years experience in ASIC Design Verification
• Experience in Graphics or Multimedia domains is a plus
• Must have excellent knowledge of ASIC Design Flow
• Experience in developing complex testbench/model in
verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing testplans and testcases
• Excellent debug skills in both functional and gate level
simulations are must.
• Experience in random test generation, coverage analysis,
failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Strong Verilog, SystemVerilog, PLI interface, SystemC or C/C
++, Perl/shell scripts or Vera programming skills.
• Experience with emulation based verification and/or
simulation acceleration techniques an asset
• Must have good communication skills and the ability and
desire to foster a team environment.
Verification Manager Job Description
Location: Hyderabad
In this highly visible role, the candidate would be responsible for
carrying out the subsystem verification of one of the 's next
generation X86 CPU projects. The candidate would work with global
verification teams to integrate the IPs and conduct the GPU subsystem
verification.
As a key leader, the candidate would drive the adoption of evolving
new verification methodologies to handle the complex integration of
CPU and Graphics capabilities within aggressive, market-driven
schedules. Understanding different verification methodologies and
ability to unify them is highly desirable. Prior experience working
with multi-site teams will be valuable. Overall exposure to the design
cycle (RTL-GDSII) is desirable.
Key responsibilities include
• Lead a team and perform project planning, estimation, tracking,
mentoring, reviews, etc.
• Plan and conduct reviews and work with other verification
organizations and development to drive upstream testing.
• Ensure that metrics are established to measure the Design
Verification processes.
• Evaluation/review of all new or existing methods, comparing them to
established procedures and standards both technical and non-technical
and champion where applicable.
• Plan and conduct test centric Post Mortem evaluation/review
• Develop and implement quality control and improvement processes
• Constantly look to improve verification productivity
SKILL REQUIREMENTS
• University graduate (BE/BTECH/MTECH) in Electronics or Computer
engineering with 10+ years professional experience including SOC/CPU/
Graphics/Multimedia Verification.
• Communication skills: excellent oral, written and presentation
skills
• Leadership experience in productivity improvement.
• Familiar with aspects of Design Verification Goals and Milestones
• Working knowledge of Verilog, System Verilog, C/C++, CVS/Subversion,
Perl/Python.
• OVM/VMM knowledge. Exposure to Assertion based verification is
needed.
• Graphics/Multimedia verification experience
• Good understanding of PCIe, Hyper-Transport (HT) protocols
• Chipset knowledge (Northbridge, Southbridge, DDR Interface, Memory
controllers)
• DFT, Debug knowledge
• Comfortable with Verilog/PLI and industry-standard EDA tools such as
VCS or NcSim
• Self-starter and quick learner and able to achieve successful
outcomes in a non-hierarchical environment, with minimal supervision
or direction.
• Detail oriented; ability to multitask through planning/organizing.
• Project management skills and experience
Design Manager Job Description
Location: Hyderabad
This is a very high scope role with complete responsibility of key
graphics and multi-media subsystem delivering to 's next generation
fusion project.
The candidate would drive the design requirements of the Graphics
subsystem in collaboration with the SOC design lead, owns the design
methodology, Synthesis and netlist delivery, timing closure and works
very closely with SOC and Physical design teams to resolve
constraints, floorplan, area and power parameters. Design manager is
responsible to work closely with the IP teams, align with SOC RTL/
Netlist schedules, conduct design reviews and signs off the final
design delivery to the SOC.
Key responsibilities
• Own subsystem design feature set – Evaluate new features and report
back to the Engineering Council
• Project planning to align to IP and SOC plans
• RTL design
• IP integration, Synthesis, Timing closure, Power Estimates
• Closely coordinate on DFT
• Drive low power initiatives
• Develop and implement quality control and improvement processes
• Constantly look to improve design productivity and proactively
identify design issues
• Sign off the design
SKILL REQUIREMENTS
• University graduate (BE/BTECH/MTECH) in Electronics or Computer
engineering with 10+ years professional experience
• ASIC design experience covering blocks, IPs, SOC
• Highly conversant with design flows, tools
• Knowledge of Power management tools/flows
• Communication skills: excellent oral, written and presentation
skills. Good negotiation skills
• Desirable experience include design knowledge of graphics,
multimedia, bus interface blocks
• Good understanding of PCIe, Hyper-Transport (HT) protocols
• Chipset knowledge (Northbridge, Southbridge, DDR Interface, Memory
controllers)
• DFT, Debug knowledge
• Hands on experience with industry standard tools and simulators
• Self-starter and quick learner and able to achieve successful
outcomes in a non-hierarchical environment, with minimal supervision
or direction.
• Detail oriented; ability to multitask through planning/organizing.
• Project management skills and experience
Implementation requirement:
Job Description
The candidate will be responsible for participating in the pre-silicon
block and system level design. The candidate will also be responsible
for Front-End chip implementation including design, synthesis and
execution flows that starts with RTL coding and ends with the delivery
of a netlist package ready for physical design. Responsible for
synthesis, netlist generation, timing and logical equivalency checks,
floorplanning, budgeting, clock methodology and timing constraint
management. Candidate will work in collaboration with Physical Design
Engineers in chip level planning and integrations.
REQUIREMENTS
- At least 7-10+ years experience in complex ASIC Design.
Direct experience in SOC or Graphics/Video is plus.
- Have in depth knowledge of entire design process from
Design specification, defining architecture, micro-architecture, RTL
design and functional verification, synthesis, Physical Design, Timing
closure, Tape-out, and post-Si debug.
- Have hands-on experience in Chiplevel Design/Integration
activities.
- Some Physical Design exposure required.
- Should be able to Lead a team, and provide Technical
mentoring and guidance to junior engineers.
- Perform Synthesis and netlisting tasks such as SDC
Development, Scan Insertion, ECO implementation, Formal Verification,
etc.
- Some exposure to DFT is a strong plus.
- Work with Physical Design team on Floor Plan, budgeting,
timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD
placement, etc.
- Should have expertise in: Cadence RTL Compiler, Design
Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath
compilers is required.
- Should have proficiency in flow development and scripting.
- Expertise in Perl and Tcl is a must.
- Should be able to work closely with RTL Designers and
Backend Physical Design teams across multiple sites.
- Must have good communication & Analytical thinking skills.
- Knowledge of chip bus interfaces such as AHB and various
standard peripherals & interfaces is a plus.
- Bachelor/Master/ Degree in Electrical or Computer
Engineering
Soc-DFT Verification –: JD
Work location- Bangalore/Hyderabad
- Preferred Education and experience: The Candidate should have a
Master's with 10+ years of experience or Bachelor of Engineering with
12+ years of experience in electronics and communication or Computer
engineering. Experience in large ASIC or processor design/
verification, C/C++ programming language, scripting languages, and
simulation and debug tools is a must. Candidate should have experience
in front-end verification of Soc-DFT features which includes MBIST,
LBIST, Boundary Scan, Scan-dump features. Processor verification
experience is desired.
Primary Purpose: Primary job function is verification of area/feature
mentioned above at the full chip level and meet grade level
expectations
Key Job Functions: Own and verify an area/feature at full chip level.
Play a key role in verification environment development (detailed test
plans, checkers, models, stimuli) and debug and root cause failures.
Good team work to ensure timely and quality deliverables. Meet grade
level expectations (technical leadership, innovation, supervision
requirement, ownership, problem solving, mentoring). Expected to
resolve issues and come up with innovative verification approaches and
solutions
PE- Logic design Engineer
Job Description:
Work as part of the logic design team to develop the architecture and
design for various next-generation digital controllers. Primary
responsibilities include generating architecture and micro-
architecture specifications as well as RTL design and synthesis of
digital controllers and other soft-macros.
Job Functions include:
• Develop reusable digital controller specification and RTL design
• Promote re-use of components across various projects
• Defining top-level and internal interface and registers
• Power/Performance analysis of designs
SMTS –Circuit Design Engineer
Job description:
In this position the person will be responsible to develop and design
the high speed circuit blocks used in Rambus proprietary advanced
development projects and standard based physical (PHY) layers. These
physical layers are the high speed mixed signal blocks, designed in
advanced technology node such as 65nm, 40nm and 28nm. The knowledge
and experience in Serializers, de-serializers, high speed receivers,
equalization techniques, samplers, transmitters, multi clock domain
custom digital data-path circuits and clocking circuits are necessary.
The designer will be responsible for all aspects of designs such as
schematic capture, layout review, simulation & analysis of critical
electrical and timing parameters, documentation and silicon bring-up.
Job involves regular interaction with worldwide team.
Skills/Qualifications:
• B.E/B-Tech in electronics engineering with atleast 5 years of
experience or
• MS/M-Tech degree in electronics/VLSI with 4+years of relevant
experience.
• The candidate should have prior experience of high speed custom
circuit design.
• Knowledge of serializer, de-serializer, bias generation, on-chip
regulation, on-chip impedance circuits and PLL is desirable.
• Experience in designing memory interfaces such as DDR2/3 or serial
links such as PCIe1/2, SATA, XAUI and CEI6 is a plus.
• Experience working in leading R&D and future technology development
projects is desirable.
• The position requires good written & verbal communication skills
Logic Design Engineering
Skills/Qualifications:,
• Bachelor / Masters degree in Electronics with at least 2 yrs
experience in Digital Design
• Knowledge of packet based protocol
• Expertise in digital designs
• Hands on experience with complete ASIC flow performed for multiple
tapeouts & post silicon debugs
• Good knowledge of Synthesis, DFT and Timing closure requirements.
• Should have good exposure to the FPGA flow.
• Should have exposure to verification flow and concepts.
The position requires good written & verbal communication skills
